An asynchronous successive approximation analog to digital converter is shown in U.S. Pat. No. 4,769,628. This analog to digital converter uses a switched voltage divider to generate a reference voltage. The reference voltage generated by the voltage divider is first buffered by an opamp before being passed to a subsequent stage or a comparator. However, this technique can present several problems.
First, when the switches are switching, the input to the opamp will float. A floating input to an opamp causes the output to drive toward saturation. Thus, a delay is required after the switches settle to allow the opamp to recover. After the opamp has settled, time must also be allowed for the comparator to settle, afterwhich the switches of a subsequent stage will take time to react to the comparator. A second problem is presented by the errors introduced by the opamps in that the input offsets of the opamps will cumulate down to the last bit. These input offsets are further aggravated by temperature instabilities associated with opamps. Thirdly, noise existing in the opamp power supplies is coupled into the reference voltages. This noise problem is compounded by the fact that an opamp that drives toward saturation and then subsequently recovers will generate transients at its power supply terminals. These transients can couple to other opamps connected to the same power supply terminals.
In U.S. Pat. No. 4,769,628 the floating opamp problem, and the resulting transient problem, are addressed by employing the embodiment shown in FIG. 3. However, this solution addresses these problems at the expense of accuracy, speed, cost and space.